View AS29F200T-55SC_4164959.PDF datasheet online --- IC-ON-LINE

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) ) ) )/ / / /$ $ $ $6 6 6 6+ + + + 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq copyright ?1998 alliance semiconductor. all rights reserved. ? $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 4 4 4 4 8 9 #589 .e ;245; .e 49# &026 # )odvk # ((3520 8 9 #589 .e ;245; .e 49# &026 # )odvk # ((3520 8 9 #589 .e ;245; .e 49# &026 # )odvk # ((3520 8 9 #589 .e ;245; .e 49# &026 # )odvk # ((3520 )hdwxuhv ? organization: 256k8 or 128k16 ? sector architecture - one 16k; two 8k; one 32k; and three 64k byte sectors - boot code sector architecturet (top) or b (bottom) - erase any combination of sectors or full chip ? single 5.00.5v power supply for read/write operations ? sector protection ? high speed 55/70/90/120 ns address access time ? automated on-chip programming algorithm - automatically programs/verifies data at specified ad- dress ? automated on-chip erase algorith - automatically preprograms/erases chip or specified sec- tors ? 10,000 write/erase cycle endurance ? hardware reset pin - resets internal state machine to read mode ? low power consumption - 20 ma typical read current - 30 ma typical program current - 300 a typical standby current - 1 a typical standby current (reset = 0) ? jedec standard software, packages and pinouts -48-pin tsop -44-pin so ? detection of program/erase cycle completion -dq7 data polling - dq6 toggle bit - ry/by output ? erase suspend/resume - supports reading data from a sector not being erased ? low v cc write lock-out below 2.8v /rjlf # eorfn # gldjudp x decoder v cc v ss cell matrix y decoder y gating data latch chip enable address latch input/output buffers sector protect command register program/erase control v cc detector erase voltage generator program voltage generator timer a0Ca16 ce oe stb stb output enable logic ry /b y we byte reset dq0Cdq15 switches a-1 3lq # duudqjhphqw 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a14 a15 a16 byte v ss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v cc a6 a5 a4 a3 a2 a1 a0 ce v ss oe dq0 dq8 dq1 dq9 dq2 dq10 44-pin so 21 22 dq3 dq11 a10 a11 a12 a13 2 ry / b y 3 nc 4 a7 1 nc 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 43 42 41 44 we a8 a9 reset a8 a9 a10 a11 a12 a13 a14 a15 a16 byte v ss dq15/a-1 dq7 dq14 nc nc we reset nc nc ry/ by nc dq2 dq10 dq3 dq11 v cc dq4 dq12 dq5 dq6 dq13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 48 47 46 45 44 43 42 41 40 39 38 37 36 35 15 16 34 33 48-pin tsop nc a7 a6 a5 a4 a3 a2 a1 a0 ce v ss oe dq0 dq8 dq1 dq9 17 18 19 20 21 22 32 31 30 29 28 27 23 24 26 25 as29f200 as29f200 6hohfwlrq # jxlgh 29f200-55 29f200-70 29f200-90 29f200-120 unit maximum access time t aa 55 70 90 120 ns maximum chip enable access time t ce 55 70 90 120 ns maximum output enable access time t oe 25 30 35 50 ns
) ) ) )/ / / /$ $ $ $6 6 6 6+ + + + $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 ? 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 5 5 5 5 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 )xqfwlrqdo # ghvfulswlrq the as29f200 is a 2 megabit, 5 volt only flash memory organized as 256k bytes of 8 bits each or 128k words of 16 bits each. for flexible erase and program capability, the 2 megabits of data is divided into 7 sectors: one 16k byte, two 8k byte, one 32k byte, and th ree 64k bytes. the 8 data appears on dq0Cdq7; the 16 data appears on dq0Cdq15. the as29f200 is offered in jedec standard 44-pin so and 48-pi n tsop packages. this device is designed to be programmed and erased in-system with a single 5.0v v cc supply. the device can also be reprogrammed in standard eprom programmers. the as29f200 offers access times of 55/70/90/120 ns, allowing 0-wait state operation of high speed microprocessors. to eliminat e bus contention the device has separate chip enable (ce ), write enable ( we ), and output enable ( oe ) controls. word mode (16 output) is selected by byte = high. the as29f200 is fully compatible with the jedec single power supply flash standard. write commands to the command register usin g standard microprocessor write timings. an internal state-machine uses register contents to control the erase and programming ci rcuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. read data from the devic e in the same manner as other flash or eprom devices. use the program command sequence to invoke the automated on-chip programming algorithm that automatically times the program pulse widths and verifies proper cell margin. use the erase command sequence to invoke the automated on-chip erase algorithm that preprograms the sector if it is not already programmed before executing the erase operation, times the erase pulse widths, and verifies proper cell margin. boot sector architecture enables the device to boot from either the top (as29f200t) or bottom (as29f200b) sector. sector erase architecture allows specified sectors of memory to be erased and reprogrammed without altering data in other sectors. a sector typically era ses and verifies within 1.6 seconds. hardware sector protection disables both program and erase operations in all or any combination of the seven sectors. the device provides background erase with erase suspend, which puts erase operations on hold to read data from a secto r that is not being erased. the chip erase command will automatically erase all unprotected sectors. a factory shipped as29f200 is fully erased (all bits = 1). the programming operation sets bits to 0. data is programmed into th e array one byte/word at a time in any sequence and across sector boundaries. a sector must be erased to change bits from 0 to 1. erase ret urns all bytes/ words in a sector to the erased state (all bits = 1). each sector is erased individually with no effect on other sectors. the device features single 5.0v power supply operation for both read and write functions. internally generated and regulated vo ltages are provided for the program and erase operations. a low v cc detector automatically inhibits write operations during power transtitions. the ry/by pin, data polling of dq7, or toggle bit (dq6) may be used to detect end of program or erase operations. the device automatically resets to the read mode after program/erase operations are completed. the as29f200 resists accidental erasure or spurious programming signals resulting from power transitions. control register arch i tecture permits alteration of memory contents only after successful completion of specific command sequences. during power up, the devi ce is set to read mode with all program/erase commands disabled when v cc is less than v lko (lockout voltage). the command registers are not affected by noise pulses of less than 5 ns on oe , ce, or we . ce and we must be logical zero and oe a logical one to initiate write commands. when the devices hardware reset pin is driven low, any program/erase operation in progress will be terminated and the internal state machine will be reset to read mode. if the reset pin is tied to the system reset circuitry and a system reset occurs during an automated on- chip program/erase algorithm, data in address locations being operated on will become corrupted and require rewriting. resettin g the device enables the systems microprocessor to read boot-up firmware from the flash memory. the as29f200 uses fowler-nordheim tunnelling to electrically erase all bits within a sector simultaneously. bytes/words are pro grammed one at a time using eprom programming mechanism of hot electron injection.
) ) ) )/ / / /$ $ $ $6 6 6 6+ + + + ? $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 6 6 6 6 )oh[leoh # vhfwru # dufklwhfwxuh in word mode, there are one 8k word, two 4k word, one 16k word, and three 32k word sectors. address range is a16Ca-1 if byte = v il ; address range is a16Ca0 if byte = v ih . ,' # 6hfwru # dgguhvv # wdeoh 2shudwlqj # prghv l = low (v ih ); v id = 12.0 0.5v; x = dont care; in 16 mode, byte = v ih . in 8 mode, byte = v il and dq8C14 is high z with dq15 = a-1(x). sector bottom boot sector architecture (as29f200b) top boot sector architecture (as29f200t) 8 16 size (kbytes) 8 16 size (kbytes) 0 00000hC03fffh 00000hC01fffh 16 00000hC0ffffh 00000hC07fffh 64 1 04000hC05fffh 02000hC02fffh 8 10000hC1ffffh 08000hC0ffffh 64 2 06000hC07fffh 03000hC03fffh 8 20000hC2ffffh 10000hC17fffh 64 3 08000hC0ffffh 04000hC07fffh 32 30000hC37fffh 18000hC1bfffh 32 4 10000hC1ffffh 08000hC0ffffh 64 38000hC39fffh 1c000hC1cfffh 8 5 20000hC2ffffh 10000hC17fffh 64 3a000hC3bfffh 1d000hC1dfffh 8 6 30000hC3ffffh 18000hC1ffffh 64 3c000hC3ffffh 1e000hC1ffffh 16 sector bottom boot sector address (as29f200b) top boot sector address (as29f200t) a16 a15 a14 a13 a12 a16 a15 a14 a13 a12 0 0000x 0 0xxx 1 00010 0 1xxx 2 00011 1 0xxx 3 001xx 1 1 0 xx 4 01xxx 11100 5 10xxx 11101 6 11xxx 1 1 1 1 x mode ce oe we a0 a1 a6 a9 reset dq id read mfr codellhlllv id hcode id read device codellhhllv id hcode read l l h a0 a1 a6 a9 h d out standby hxxxxxxhhigh z output disable l hhxxxxhhigh z write l h l a0 a1 a6 a9 h d in enable sector protect l v id pulse/l l h l v id hx sector unprotect l v id pulse/ll hhv id hx verify sector protect l l h l h l v id hcode temporary sector unprotect xxxxxxxv id x hardware reset xxxxxxxl high z
) ) ) )/ / / /$ $ $ $6 6 6 6+ + + + $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 ? 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 7 7 7 7 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 0rgh # ghilqlwlrqv 5($' # frghv key: l =low (v ih ); x =dont care; t = top; b = botto item description id mfr code, device code selected by a9 = v id (11.5C12.5v), ce = oe = a1 = a6 = l, enabling outputs. when a0 is low (v il ) the output data = 52h, a unique mfr. code for alliance semiconductor flash products. when a0 is high (v ih ), d out represents the device code for the as29f200. read mode selected with ce = oe = l, we = h. data is valid in t acc time after addresses are stable, t ce after ce is low and t oe after oe is low. standby selected with ce = h. part is powered down, and i cc reduced to <2.0 ma for ttl input levels. if activated during an automated on-chip algorithm, the device completes the operation before entering standby. output disable part remains powered up; but outputs disabled with oe pulled high. write selected with ce = we = l, oe = h. accomplish all flash erasure and programming through the command register. contents of command register serve as inputs to the internal state machine. address latching occurs on the falling edge of we or ce , whichever occurs late . data latching occurs on the rising edge we or ce , whichever occurs first. filters on we prevent spurious noise events from appearing as write commands. enable sector protect hardware protection circuitry implemented with external programming equipment causes the device to disable program and erase operations for specified sectors. sector unprotect disables sector protection for all sectors using external programming equipment. all sectors must be protected prior to sector unprotection. ve r i f y sector protect verifies write protection for sector. sectors are protected from program/erase operations on commercial programming equipment. determine if sector protection exists in a system by writing the id read command sequence and reading location xxx02h, where address bits a12C16 select the defined sector addresses. a logical 1 on dq0 indicates a protected sector; a logical 0 indicates an unprotected sector. te m p o r a r y sector unprotect temporarily disables sector protection for in-system data changes to protected sectors. apply +12v to reset to activate sector unprotect mode. during temporary sector unprotect mode, program protected sectors by selecting the appropriate sector address. all protected sectors revert to protected state on removal of +12v from reset . reset resets the write and erase state machine to read mode. if device is programming or erasing when reset = l, data may be corrupted. deep power down hold reset low to enter deep power down mode ( < 10 a cmos). recovery time to active mode is 1.5 s. mode a16Ca12 a6 a1 a0 code mfr code (alliance semiconductor) x l l l 52h device code 8 t boot x llh51h 8 b boot x llh57h 16 t boot x l l h 2251h 16 b boot x l l h 2257h sector protection sector address l h l 01h protected 00h unprotected
) ) ) )/ / / /$ $ $ $6 6 6 6+ + + + ? $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 8 8 8 8 :ulwh # rshudwlrq # vwdwxv ? toggles with oe or ce only for erasing or erase suspended sector addresses. ? toggles only if dq5 = 1 and address applied is within sector that exceeded timing limits. dq8Cdq15 = dont care in 16 mode. &rppdqg # ghilqlwlrqv status dq7 dq6 dq5 dq3 dq2 ry/by in progress auto programming (byte/word) dq 7 toggle 0 0 no toggle 0 program/erase in auto erase 0 toggle 0 1 toggle ? 0 erase suspend mode read erasing sector 1 no toggle 0 0 toggle 1 read non-erasing sector data data data data data 1 program in erase suspend dq 7 toggle 0 0 toggle ? 0 exceeded time limits auto programming (byte/word) dq 7 toggle 1 na no toggle 1 program/erase in auto erase 0 toggle 1 1 toggle ? 1 program in erase suspend dq 7 toggle 1 na no toggle ? 1 item description reset/read initiate read or reset operations by writing the read/reset command sequence into the command register. this allows the microprocessor to retrieve data from the memory. device remains in read mode until command register contents are altered. device automatically powers up in read/reset state. this feature allows only reads, therefore ensuring no spurious memory content alterations during power up. id read as29f200 provides manufacturer and device codes in two ways. external prom programmers typically access the device codes by driving +12v on a9. as29f200 also contains an id read command to read the device code with only +5v, since multiplexing +12v on address lines is generally undesirable. initiate device id read by writing the id read command sequence into the command register. follow with a read sequence from address xx00h to return mfg code. follow id read command sequence with a read sequence from address xx01h to return device code. to verify write protect status on sectors, read address xx02h. sector addresses a16Ca12 produce a 1 on dq0 for protected sector and a 0 for unprotected sector. exit from id read mode with read/reset command sequence. hardware reset holding reset low for 500 ns resets the device, terminating any operation in progress; data handled in the operation is corrupted. the internal state machine resets 20 s after reset is driven low. ry/by remains low until the reset operation is completed. after reset is set high, there is a delay of 1.5 s for the device to permit read operations.
) ) ) )/ / / /$ $ $ $6 6 6 6+ + + + $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 ? 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 9 9 9 9 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 byte/word programming programming the as29f200 is a four bus cycle operation performed on a byte-by-byte or word- by-word basis. two unlock write cycles precede the program setup command and program data write cycle. upon execution of the program command, no additional cpu controls or timings are necessary. addresses are latched on the falling edge of ce or we (whichever is last); data is latched on the rising edge of ce or we , (whichever is first). the as29f200s automated on-chip program algorithm provides adequate internally-generated programming pulses and verifies the programmed cell margin. check programming status by sampling data on the data polling (dq7), toggle bit (dq6), or ry/ by pin. the as29f200 returns the equivalent data that was written to it (as opposed to complemented data), to complete the programming operation. the as29f200 ignores commands written during programming. a hardware reset occurring during programming may corrupt the data at the programmed location. as29f200 allows programming in any sequence, across any sector boundary. changing data from 0 to 1 requires an erase operation. attempting to program data 0 to 1 results in dq5 = 1 (exceeded programming time limits); reading this data after a read/reset operation returns a 0. when programming time limit is exceeded, dq5 reads high, and dq6 continues to toggle. in this state, a reset command returns the device to read mode. chip erase chip erase requires six bus cycles: two unlock write cycles; a setup command, two additional unlock write cycles; and finally the chip erase command. chip erase does not require logical 0s written prior to erasure. when the automated on-chip erase algorithm is invoked with the chip erase command sequence, as29f200 automatically programs and verifies the entire memory array for an all-zero pattern prior to erase. the as29f200 returns to read mode upon completion of chip erase unless dq5 is set high as a result of exceeding time limit. sector erase sector erase requires six bus cycles: two unlock write cycles, a setup command, two additional unlock write cycles, and finally the sector erase command. determine the sector to be erased by addressing any location in the sector. this address is latched on the falling edge of we ; the command, 30h is latched on the rising edge of we . the sector erase operation begins after a 80 s time-out. to erase multiple sectors, write the sector erase command to each of the addresses of sectors to erase after following the six bus cycle operation above. timing between writes of additional sectors must be <80 s, or the as29f200 ignores the command and erasure begins. during the time-out period any falling edge of we resets the time-out. any command (other than sector erase or erase suspend) during time-out resets the as29f200 to read mode, and the device ignores the sector erase command string. erase such ignored sectors by restarting the sector erase command on the ignored sectors. the entire array need not be written with 0s prior to erasure. as29f200 writes 0s to the entire sector prior to electrical erase; writing of 0s affects only selected sectors, leaving non-selected sectors unaffected. as29f200 requires no cpu control or timing signals during sector erase operations. automatic sector erase begins after erase time-out from the last rising edge of we from the sector erase command stream and ends when the data polling (dq7) is logical 1. data polling address must be performed on addresses that fall within the sectors being erased. as29f200 returns to read mode after sector erase unless dq5 is set high by exceeding the time limit. item description
) ) ) )/ / / /$ $ $ $6 6 6 6+ + + + ? $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 : : : : 6wdwxv # rshudwlrqv erase suspend erase suspend allows interruption of sector erase operations to perform data reads from a sector not being erased. erase suspend applies only during sector erase operations, including the time-out period. writing an erase suspend command during sector erase time-out results in immediate termination of time-out period and suspension of erase operation. as29f200 ignores any commands during erase suspend other than the reset or erase resume commands. writing erase resume continues erase operations. addresses are dont care when writing erase suspend or erase resume commands. as29f200 takes 0.2C15 s to suspend erase operations after receiving erase suspend command. check completion of erase suspend by polling ry/by . check dq2 in conjunction with dq6 to determine if a sector is being erased. as29f200 ignores redundant writes of erase suspend. as29f200 defaults to erase-suspend-read mode while an erase operation has been suspended. while in erase-suspend-read mode as29f200 allows reading data from or programming data to any sector not undergoing sector erase. write the resume command 30h to continue operation of sector erase. as29f200 ignores redundant writes of the resume command. as29f200 permits multiple suspend/resume operations during sector erase. sector protect when attempting to write to a protected sector, data polling and toggle bit 1 (dq6) are activated for about <1 s. when attempting to erase a protected sector, data polling and toggle bit 1 (dq6) are activated for about <5 s. in both cases, the device returns to read mode without altering the specified sectors. ready/busy ry/by indicates whether an automated on-chip algorithm is in progress (ry/by = low) or completed (ry/by = high). the device does not accept program/erase commands when ry/by = low. ry/by = high when device is in erase suspend mode. ry/by is an open drain output, enabling multiple ry/by pins to be tied in parallel with a pull up resistor to v cc . data polling (dq7) only active during automated on-chip algorithms or sector erase time outs. dq7 reflects complement of data last written when read during the automated on-chip algorithm (0 during erase algorithm); reflects true data when read after completion of an automated on-chip algorithm (1 after completion of erase agorithm). toggle bit (dq6) active during automated on-chip algorithms or sector erase time outs. dq6 toggles when ce or oe toggles, or an erase resume command is invoked. dq6 is valid after the rising edge of the fourth pulse of we during programming; after the rising edge of the sixth we pulse during chip erase; after the last rising edge of the sector erase we pulse for sector erase. for protected sectors, dq6 toggles for only <1 s during writes, and <5 s during erase (if all selected sectors are protected). exceeding time limit (dq5) indicates unsuccessful completion of program/erase operation (dq5 = 1). data polling remains active; ce powers the device down to 2 ma. if dq5 = 1 during chip erase, all or some sectors are defective; during byte programming, the entire sector is defective; during sector erase, the sector is defective (in this case, reset the device and execute a program or erase command sequence to continue working with functional sectors). attempting to program 0 to 1 will set dq5 = 1. item description
) ) ) )/ / / /$ $ $ $6 6 6 6+ + + + $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 ? 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq ; ; ; ; $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 &rppdqg # irupdw 1 bus operations defined in "mode definitions," on page 4. 2 reading data from or programming data to non-erasing sectors allowed in erase suspend mode. 3 address bit a15 = x = dont care for all address commands except program address and sector address. 4 address bit a16 = x = dont care for all address commands except program address and sector address. 5 system should generate address patterns: 16 mode - 5555h or 2aaah to address a0Ca14; 8 mode - aaaah or 5555h to address a-1C a14. 6a 0 = 0, a 1 = 1, a 6 = 0 for sector protect verify; sector selected on a16-a12. sector erase timer (dq3) checks whether sector erase timer window is open. if dq3 = 1, erase is in progress; no commands will be accepted. if dq3 = 0, the device will accept sector erase commands. check dq3 before and after each sector erase command to verify that the command was accepted. toggle bit 2 (dq2) during sector erase, dq2 toggles with oe or ce only during an attempt to read a sector being erased. during chip erase, dq2 toggles with oe or ce for all addresses. if dq5 = 1, dq2 toggles only at sector addresses where failure occurred, and will not toggle at other sector addresses. use dq2 in conjunction with dq6 to determine whether device is in auto erase or erase suspend mode. command sequence required bus cycles 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus read/write cycle 5th bus write cycle 6th bus write cycle address data address data address data address data address data address data reset/read 1 xxxxh f0h read address read data reset/read 16 4 5555h aah 2aaah 55h 5555h f0h read address read data 8 aaaah 5555h aaaah autoselect id read 16 4 5555h aah 2aaah 55h 5555h 90h 01h 2251h (t) 2257h (b) 8 aaaah 5555h aaaah 02h 51h (t) 57h (b) 16/8 00h mfr code 52h 16 xxx02h 01 = protected 00 = unprotected 8 xxx04h program 16 4 5555h aah 2aaah 55h 5555h a0h program address program data 8 aaaah 5555h aaaah chip erase 16 6 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h 8 aaaah 5555h aaaah aaaah 5555h aaaah sector erase 16 6 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sector address 30h 8 aaaah 5555h aaaah aaaah 5555h sector erase suspend 1 xxxxh b0h sector erase resume 1 xxxxh 30h
) ) ) )/ / / /$ $ $ $6 6 6 6+ + + + ? $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 < < < < $xwrpdwhg # rq 0 fkls # surjudpplqj # dojrulwkp $xwrpdwhg # rq 0 fkls # hudvh # dojrulwkp ? the system software should check the status of dq3 prior to and following each subsequent sector erase command to ensure command completion. the device may not have accepted the command if dq3 is high on second status check. write program command sequence (see below) data poll device verify byte? programming completed 5555h/aah 2aaah/55h 5555h/a0h program address/program data program command sequence 16 mode (address/command): no yes 5555h/aah 2aaah/55h 5555h/80h chip erase command sequence 5555h/aah 2aaah/55h 5555h/10h sector erase command sequence erase complete sector address/30h sector address/30h sector address/30h optional multiple sector erase commands ? 16 mode (address/command): 16 mode (address/command): 5555h/aah 2aaah/55h 5555h/80h 5555h/aah 2aaah/55h data polling or toggle bit successfully completed write erase command sequence (see below)
) ) ) )/ / / /$ $ $ $6 6 6 6+ + + + $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 ? 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 43 43 43 43 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 '$7$ # sroolqj # dojrulwkp ? va = byte address for programming. va = any of the sector addresses within the sector being erased during sector erase. va = valid address equals any non-protected sector group address during chip erase. ? dq7 rechecked even if dq5 = 1 because dq5 and dq7 may not change simultaneously. 7rjjoh # elw # dojrulwkp ? dq6 rechecked even if dq5 = 1 because dq6 may stop toggling when dq5 changes to 1. read byte (dq0Cdq7) address = va ? read byte (dq0Cdq7) address = va no done no no ? yes fail yes ? yes done dq7 = data ? dq5 = 1 ? dq7 = data ? ? read byte (dq0Cdq7) address = dont care read byte (dq0Cdq7) address = dont care no done yes yes yes fail no no done dq6 = toggle ? dq6 = toggle ? ? dq5 = 1 ?
) ) ) )/ / / /$ $ $ $6 6 6 6+ + + + ? $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 44 44 44 44 7hpsrudu\ # vhfwru # xqsurwhfw 7hpsrudu\ # vhfwru # xqsurwhfw # zdyhirup # '& # hohfwulfdo # fkdudfwhulvwlfv 9 && # #813 318 9 1 not more than one output tested simultaneously. duration of the short circuit must not be >1 second. out = 0.5v was selected to avoid test problems caused by tester ground degradation. (this parameter is sampled and not 100% tested, but guaranteed by characterization.) 2the i cc current listed includes both the dc operating current and the frequency dependent component (@ 6 mhz). the frequency component typically is less than 2 ma/mhz with oe at v ih . 3i cc active while program or erase operations are in progress. .h\ # wr # vzlwfklqj # zdyhirupv parameter symbol all speeds unit v id rise and fall time t vidr 500 (min) ns reset# setup time for temporary sector unprotect t rsp 4 (min) s parameter symbol test conditions min max unit input load current i li v in = v ss to v cc , v cc = v ccmax -1a a9 input load current i lit v cc = v ccmax , a9 = 12.5v 90 a output leakage current i lo v out = v ss to v cc , v cc = v ccmax -1a output short circuit current 1 i os v out = 0.5v - 200 ma active current, read @ 6mhz 2 i cc ce = v il , oe = v ih -40ma active current, program/erase 3 i cc2 ce = v il , oe = v ih -60ma standby current (ttl compatible) i sb1 ce = oe = v ih , v cc = v ccmax -400a deep power down i sb2 rp = 0v - 1 a input low voltage v il -0.5 0.8 v input high voltage v ih 2.0 v cc + 0.3 v output low voltage v ol i ol = 5.8ma, v cc = v cc min -0.45v output high level v oh1 i oh = -2.5 ma, v cc = v cc min 2.4 - v v oh2 i oh = -100 a, v cc = v cc min v cc - 0.4 - v low v cc lock out voltage v lko 2.8 4.2 v input hv select voltage v h 11.5 12.5 v reset ce we ry/ by t rsp t vidr t vidr program/erase command sequence 0 or 1.8v 10v undefined output/don?t care falling input rising input
) ) ) )/ / / /$ $ $ $6 6 6 6+ + + + $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 ? 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 45 45 45 45 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 0d[lpxp # qhjdwlyh # ryhuvkrrw # zdyhirup 0d[lpxp # srvlwlyh # ryhuvkrrw # zdyhirup $& # sdudphwhuv =# uhdg # f\foh 5hdg # zdyhirup jedec symbol std symbol parameter -55 -70 -90 -120 unit minmaxminmaxminmaxminmax t avav t rc read cycle time 55 - 70 - 90 - 120 - ns t av q v t acc address to output delay - 55 - 70 - 90 - 120 ns t elqv t ce chip enable to output - 55 - 70 - 90 - 120 ns t glqv t oe output enable to output - 25 - 30 - 35 - 50 ns t ehqz t df chip enable to output high z - 15 - 20 - 20 - 30 ns t ghqz t df output enable to output high z - 15 - 20 - 20 - 30 ns t axqx t oh output hold time from addresses, first occurrence of ce or oe 0-0-0-0-ns t elfl/elfh ce to byte transition low/high-5-5-5-5ns t phqv t pwh reset high to output delay - 1.5 - 1.5 - 1.5 - 1.5 s t bdel byte switching to valid data - 55 - 70 - 90 - 120 ns t flqz byte low to dq8Cdq15 tri-state 30 - 30 - 35 - 50 - ns 20 ns 20 ns 20 ns -2.0v -0.5v +0.8v 20 ns 20 ns 20 ns v cc +2.0v v cc +0.5v +2.0v addresses stable addresses t rc t acc t oe t oeh t ce t oh t df ce oe we outputs high z high z output valid t elfl/elfh t pwh byte reset t bdel
) ) ) )/ / / /$ $ $ $6 6 6 6+ + + + ? $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 46 46 46 46 $& # sdudphwhuv # 3 # zulwh # f\foh :( # frqwuroohg :ulwh # zdyhirup :( # frqwuroohg jedec symbol std symbol parameter -55 -70 -90 -120 unit min max min max min max min max t avav t wc write cycle time 55 - 70 - 90 - 120 - ns t av w l t as address setup time 0-0-0-0- ns t wlax t ah address hold time 40 - 45 - 45 - 50 - ns t dvw h t ds data setup time 25 - 30 - 45 - 50 - ns t whdx t dh data hold time 0-0-0-0- ns t oes output enable setup time 0 - 0 - 0 - 0 - ns t oeh output enable hold time: read 0 - 0 - 0 - 0 - ns output enable hold time: toggle and data polling 10 - 10 - 10 - 10 - ns t ready reset pin low to read mode 20 - 20 - 20 - 20 - s t rp reset 500-500-500-500- ns t ghwl t ghwl read recover time before write0-0-0-0- ns t elwl t cs ce setup time 0 - 0 - 0 - 0 - ns t wheh t ch ce hold time 0-0-0-0- ns t wlwh t wp write pulse width 35 - 35 - 45 - 50 - ns t whwl t wph write pulse width high 20 - 20 - 20 - 20 - ns t whwh1 t whwh1 programming pulse time 50 - 50 - 50 - 50 - s t whwh2 t whwh2 erase pulse time 0.3-0.3-0.3-0.3- sec addresses ce oe we data v ss t wc t as t ah t ghwl ; t oes t wp t cs t wph t dh t whwh1 or 2 t ds dq 7d out 5555h program address program address 3rd bus cycle t ch data polling a0h program data
) ) ) )/ / / /$ $ $ $6 6 6 6+ + + + $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 ? 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 47 47 47 47 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 $& # sdudphwhuv3zulwh # f\foh #5 &( # frqwuroohg :ulwh # zdyhirup #5 &( # frqwuroohg jedec symbol std symbol parameter -55 -70 -90 -120 unit min max min max min max min max t avav t wc write cycle time 55 - 70 - 90 - 120 - ns t av e l t as address setup time 0 - 0 - 0 - 0 - ns t elax t ah address hold time 40 - 45 - 45 - 50 - ns t dveh t ds data setup time 30 - 30 - 45 - 50 - ns t ehdx t dh data hold time 0 - 0 - 0 - 0 - ns t oes output enable setup time 0 - 0 - 0 - 0 - ns t oeh output enable hold time: read 0 - 0 - 0 - 0 - ns output enable hold time: toggle and data polling 10-10-10-10- ns t ghel t ghel read recover time before write0-0-0-0- ns t wlel t ws we setup time 0 - 0 - 0 - 0 - ns t ehwh t wh we hold time 0-0-0-0- ns t eleh t cp ce pulse width 35 - 35 - 45 - 50 - ns t ehel t cph ce pulse width high 20 - 20 - 20 - 20 - ns t whwh1 t whwh1 programming pulse time 50 - 50 - 50 - 50 - s t whwh2 t whwh2 erase pulse time 0.3 - 0.3 - 0.3 - 0.3 - sec addresses we oe ce data program address 5555h program address a0h program dq 7d out t wc t as t ah t cp t cph t dh t ds t whwh1 or 2 data polling data t ghel , t oes t ws t wh
) ) ) )/ / / /$ $ $ $6 6 6 6+ + + + ? $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 48 48 48 48 (udvh # zdyhirup e 49# prgh # 5(6(7 # zdyhirup 5< 2 %< # zdyhirup addresses ce oe we data 5555h 2ah 5555h 5555h 2ah sector address t wc t as t ah t ghwl aah 55h 80h aah 55h 30h 10h for chip erase t wp t cs t wph t dh t ds t wc ce ry / b y reset t rp t ready ce we ry/by rising edge of last we signal program/erase operation tri-stated open-drain
) ) ) )/ / / /$ $ $ $6 6 6 6+ + + + $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 ? 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 49 49 49 49 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 '$7$ # sroolqj # zdyhirup 7rjjoh # elw # zdyhirup (udvh # dqg # surjudpplqj # shuirupdqfh parameter limits unit min typical max sector erase and verify-1 time (excludes 00h programming prior to erase) - 1.6 - sec word programming time - 60 - s byte program time - 60 - s chip programming time - 7.5 - sec erase/program cycles - - 10,000 cycles ce oe we dq7 t ch t oh t whwh1 or 2 t oe t oeh t ce t df high z input dq7 output dq 7 output ce we oe dq6 t oeh t dh t oe
) ) ) )/ / / /$ $ $ $6 6 6 6+ + + + ? $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 4: 4: 4: 4: $& # whvw # frqglwlrqv 5hfrpphqghg # rshudwlqj # frqglwlrqv $evroxwh # pd[lpxp # udwlqjv stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. exposure to absolute max- imum rating conditions for extended periods may affect reliability. /dwfkxs # wrohudqfh # includes all pins except v cc . test conditions: v cc = 5.0v, one pin at a time. parameter symbol min typical max unit supply voltage v cc +4.5 5.0 +5.5 v v ss 000v input voltage v ih 2.0 - v cc + 0.5 v v il C0.5 - 0.8 v parameter symbol min max unit input voltage (input or dq pin) v in C2.0 +7.0 v input voltage (a9 pin, oe , reset )v in C2.0 +13.0 v power supply voltage v cc -0.5 +5.5 v operating temperature t opr C55 +125 c storage temperature (plastic) t stg C65 +150 c short circuit output current i out -200ma parameter min max unit input voltage with respect to v ss on a9, oe , and reset pin -1.0 +13.0 v input voltage with respect to v ss on all dq, address and control pins -1.0 v cc +1.0 v current -100 +100 ma 100 pf* device under test *including scope and jig capacitance v ss test condition -170 -200 unit output load 1 ttl gate input rise and fall times 5 ns input pulse levels 0.0-2.0 v input timing measurement reference levels 1.0 v output timing measurement reference levels 1.0
) ) ) )/ / / /$ $ $ $6 6 6 6+ + + + $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 ? 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 4; 4; 4; 4; $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 7623 # slq # fdsdflwdqfh 62 # slq # fdsdflwdqfh 'dwd # uhwhqwlrq symbol parameter test setup typ max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 8 10 f symbol parameter test setup typ max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 8 10 f parameter te m p. (c) min unit minimum pattern data retention time 150 10 years 125 20 years
) ) ) )/ / / /$ $ $ $6 6 6 6+ + + + ? $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 4< 4< 4< 4< 3dfndjh # glphqvlrqv e f g 1 2 3 4 5 6 7 8 9 10 11 12 13 14 48 47 46 45 44 43 42 41 40 39 38 37 36 35 15 16 34 33 17 18 19 20 21 22 32 31 30 29 28 27 23 24 26 25 b a c d i h j 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 2 3 4 1 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 43 42 41 44 p n o q m r s t u w 48-pin tsop 44-pin so 0C5 0C8 48-pin tsop min (mm) max (mm) a1.20 b0.25 c0.500.70 d 0.1 0.21 e 18.30 18.50 f 19.80 20.20 g 11.90 12.10 h0.951.05 i0.050.15 j0.50 44-pin so min (mm) max (mm) m 28.00 28.40 n0.350.50 o0.100.35 p2.172.45 q2.80 r1.27 s 13.10 13.50 t 15.70 16.30 u0.061.00 w0.100.21
) ) ) )/ / / /$ $ $ $6 6 6 6+ + + + $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 $6 5< ) 533 ? 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 53 53 53 53 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 ',' #4407333<0 $ 1#72:233 2ughulqj # frghv 3duw # qxpehulqj # v\vwhp package \ access time 55 ns (commercial/industrial) 70 ns (commercial/industrial) 90 ns (commercial/industrial) 120 ns (commercial/industrial) tsop, 1220 mm, 48-pin as29f200b-55tc as29f200b-55ti as29f200b-70tc as29f200b-70ti as29f200b-90tc as29f200b-90ti as29f200b-120tc as29f200b-120ti as29f200t-55tc as29f200t-55ti as29f200t-70tc as29f200t-70ti as29f200t-90tc as29f200t-90ti as29f200t-120tc as29f200t-120ti so, 600 mil wide, 44-pin as29f200b-55sc as29f200b-55si as29f200b-70sc as29f200b-70si as29f200b-90sc as29f200b-90si as29f200b-120sc as29f200b-120si AS29F200T-55SC as29f200t-55si as29f200t-70sc as29f200t-70si as29f200t-90sc as29f200t-90si as29f200t-120sc as29f200t-120si as29 x 200 x Cxxx x c flash eeprom prefix f = 5v lv = 3 v ll = 2.5v device number b (bottom) or t (top) boot block address access time package: s= so t= tsop temperature range c = commercial, 0c to 70 c i = industrial, -40c to 85c

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